This invention relates to a MOS integrated circuit including an improved protective circuit adapted to protect the MOS integrated circuit from an irregular input signal which is inputted to a MOS transistor at an input stage of a MOS IC body of the MOS integrated circuit.
With the advent of high-density, high speed MOS integrated circuits there is a tendency that, for example, a silicon oxide film which is used between a substrate and the gate electrode of a MOS transistor becomes thinner and thinner. There is, however, a fear that the gate electrode of a MOS transistor which is the input stage of the MOS integrated circuit will be destroyed by an external surge pulse signal. To avoid such a disadvantage a protective circuit is connected between the gate electrode of the MOS transistor and a signal input terminal. The protective circuit is incorporated in IC form into the MOS integrated circuit, the equivalent circuit of which is shown in FIG. 1. In the circuit shown in FIG. 1 a MOS transistor Q.sub.1 for a driver and MOS transistor Q.sub.2 for a load constitute an inverter at the input stage of the MOS integrated circuit and a protective MOS transistor Q.sub.3 is connected between the gate electrode of the MOS transistor Q.sub.1 and has a drain electrode connected to the gate of the MOS transistor Q.sub.1 and a source electrode connected to ground. A resistor R is connected between the gate of the MOS transistor Q.sub.1 and a signal input terminal Inp. The protective MOS transistor Q.sub.3 constitutes, together with the resistor R, a protective circuit.
The breakdown of the gate is caused dependent upon the level of a peak value and sharp rise of an input surge pulse signal to the signal input terminal Inp. The protective MOS transistor Q.sub.3 performs an effective protective function against the peak value of surge voltage since the drain withstand voltage is involved. A C-R circuit comprises the resistor R and a stray capacitance Cs present between a junction of the gate of the MOS transistor Q.sub.1 and drain of the protective transistor Q.sub.3 and ground and serves to make the sharp rise of the surge pulse gentle. In this case, the greater the CR value of the C-R circuit, the more pronounced the protection effect of the C-R circuit. Recent tendency is toward a MOS integrated circuit of SOS (silicon on sapphire) construction in which an island-like semiconductor layer is formed on an insulating substrate and includes elements such as transistors, diodes, resistors, capacitors, etc. Such an SOS structure permits fabrication of a high-speed MOS integrated circuit, since it can greatly reduce unnecessary pn junctions and stray capacitance of connections. Furthermore, a high-density MOS integrated circuit can be obtained, because elements can be readily and positively separated from each other. However, the great reduction of the stray capacitance causes the CR value of the CR circuit in the protective circuit to be reduced, causing a disadvantage from the standpoint of protection against a surge input pulse. A protective circuit in the MOS integrated circuit of SOS construction will be explained by referring to FIG. 1. An electrostatic capacitance C between ground and the gate, source and drain regions of the MOS transistors Q.sub.1, Q.sub.2 and Q.sub.3 made of island-like semiconductor layers formed on the insulating substrate is determined as follows. The capacitance between the gates of the MOS transistors and ground is determined by the thickness of the insulating substrate and thickness of an oxide film, such as an SiO.sub.2 film, formed in the semiconductor structure, while the capacitance between the source and drain regions of the MOS transistors and ground is determined by the thickness of the insulating substrate. Since the resistor R is formed directly on the insulating substrate, its capacitance is determined only by a thickness of about 300 to 500.mu. from the insulating substrate and becomes an extremely small value, failing to sufficiently absorb the sharp rise of a surge pulse. As a result, the gate electrode of the MOS transistor Q.sub.1 at the input stage is exposed to an increased risk of destruction.